Dr. Ted Szymanski

Overview of CISC/RISC microprocessors; performance metrics; instruction set design; processor and memory acceleration techniques; pipelining; scheduling; instruction level parallelism; memory hierarchies; multiprocessor structures; storage systems; interconnection networks.
Three lectures, one tutorial, one lab every other week; first term
Prerequisite(s): COMPENG 3DR4
Antirequisite(s): COMPSCI 2GA3, SFWRENG 2GA3, 3GA3

3 unit(s)
Staff

Overview of CISC/RISC microprocessors and their evolution; performance metrics; instruction set design; microprogramming and hardwired control; processor and memory acceleration techniques; memory hierarchies; multiprocessor structures and their performance.

3 unit(s)
This course addresses the topics of communications, “Quality of Service” (QoS), and efficiency in networks, including the Internet and wireless networks. The first part of the course will focus on an introduction to basic networks, basic switches and routers, network routing algorithms, and scheduling algorithms. The second part will focus on basic queuing systems and traffic models. The third will look at several classic network optimization problems.

3 unit(s)
T. Szymanski

Traffic Engineering in telecommunication networks is rapidly evolving in response to the need to provide quality of service guarantees for data traffic in the internet. The course will focus on selected topics in the field, including the mathematical analysis of queueing systems, traffic models, large-scale switching system architectures, switch scheduling algorithms for QOS and network routing for QOS.